IBM to Reduce Performance Gap Between I/O and Processors
- By Scott Bekker
KIRKLAND, WASH. – IBM Corp. is working to reduce the performance gap between industry standard PCI system buses and Intel Corp.’s microprocessors, the company said here Monday at the IBM Center for Microsoft Technology.
The changes are part of a new core chipset, code-named Summit, that will ship in future Netfinity servers and be honed for Windows 2000. IBM plans to announce the core chipset early next year.
Summit, which is built around the microprocessor, memory and I/O, will provide hardware support for multi-processor hot swapping, partitioning, and a scalability port that connects to other Summit chip sets.
Since shared I/O system buses traditionally have been a bottleneck plaguing the performance of microprocessors, IBM is concentrating heavily on I/O with Summit.
The recent throughput jump from 66-MHz to 100-MHz PCI buses helps close the performance gap, but as processors rapidly increase in speed, buses will continue to be the bottleneck.
"The Input/Output is the weak link," says Tom Bradicich, the program director for Netfinity architecture. "The system is only as fast its weakest link."
Currently, microprocessors are adhering to Moore’s Law, which states that silicon technology will double in performance capability every 18 months.
"As far as we can see, that’s going to continue for at least the next 5 to 10 years," says Phil Hester, vice president and CTO of IBM’s personal systems group.
As a result, Bradicich says today’s very fast microprocessors end up waiting for I/0, albeit waiting fast. Also, the shared bus approach suffers from performance degradation when you scale up.
To reduce this performance gap between blazing processors and poky I/O, IBM is including the Infiniband technology, which includes OS/390 Channel I/O technology that is built into IBM Windows servers, with the Summit core chipset.
Infiniband enables a Channel or Switch form of I/O, thus eliminating the sharing of system buses among I/O devices and enabling direct channel connections to multiple I/O devices.
Bradicich explains that by moving away from the shared bus approach, Channel I/O virtually eliminates performance bottlenecks, scales up with little performance degradation, and provides dedicated point to point connections to the processor, as well as other I/O equipment, such as storage and network devices.
A specification for Infiniband should be completed in January 2000. Prototypes will appear in early 2001, with finished products coming to market in the third or fourth quarter.
Despite these changes, the PCI bus won’t be added to the endangered species list for quite some time. Instead, PCI will reside inside the same boxes as Channel I/O – much the same way that ISA and PCI both have been standard in the same systems for several years. – Thomas Sullivan
About the Author
Scott Bekker is editor in chief of Redmond Channel Partner magazine.